module data_mem_top(clk,rst,DataAddress,DataWrite,MemWrite,MemRead,ReadData);
  
  input clk,rst,MemWrite,MemRead;
  input [7:0] DataAddress,DataWrite;
  
  output [7:0] ReadData;

  reg [7:0] data_RAM[63:0];
  
  reg [7:0] ReadData;
    
   always @(posedge clk)
  
  begin
    
    if(MemWrite)
      data_RAM[DataAddress] <= DataWrite;
      
    else if(MemRead)
      ReadData <= data_RAM[DataAddress];   
    
  
  end 
  
endmodule
